1. Field of the Invention
The present invention relates to a CDMA (Code Division Multiple Access) modulation and demodulating method and a communication system using the same, and more particularly relates to a CDMA modulation and demodulation method and a communication system using the same which simultaneously transmits a pilot signal and a data signal through the same channel.
2. Description of the Prior Art
FIG. 1 shows a block diagram of a CDMA QPSK modulator in accordance with a conventional techniques.
Multipliers 101A and 101B multiply the inphase data signal d.sub.I (t) and the quadrature data signal d.sub.Q (t) by the walsh code Wd(t). Then, adders 102A and 102B add each signal from multipliers 101A and 101B to the pilot signal Wp(t). Multipliers 103A and 104A multiply the inphase data signal from the adder 102A by the inphase pseudo noise sequence and carrier signal cos(.omega.ct+.phi.), which generates an inphase signal. Multipliers 103B and 104B multiply the quadrature data signal from the adder by the quadrature pseudo noise sequence and the carrier signal sin(.omega.ct+.phi.), which generates a quadrature signal. The carrier signal multiplied by the quadrature signal has a 90.degree. phase difference from the carrier signal multiplied by the inphase signal. The adder 105 adds the inphase signal to the quadrature signal and generates transmission signal. Here, the QPSK modulation and demodulation method is used as a signal modulation and demodulation method.
FIG. 2 shows a block diagram of a CDMA QPSK demodulator in accordance with a conventional technique.
The demodulator consists of a pilot signal detecting part and a data signal recovering part.
The transmitted signal is received by the antenna (not shown in FIG. 2). The multiplier 201A multiplies the received signal from the antenna by cos (.omega.ct+.phi.) and then undergoes low pass filtering by the LPF (Low Pass Filter) 202A, which generates a baseband inphase signal. Also, the multiplier 201B multiplies the received signal by sin(.omega.ct+.phi.) and then undergoes low pass filtering by LPF (Low Pass Filter) 202B, which generates baseband quadrature signal.
Multipliers 203A and 203C multiply the inphase signal I(t) by the inphase and the quadrature pseudo noise sequence P.sub.I (t) and P.sub.Q (t), which generate despreading inphase signals. Multipliers 203B and 203D multiply the quadrature signal by the inphase and the negative quadrature pseudo noise sequence P.sub.I (t) and P.sub.Q (t), which generates despreading quadrature signals. The adder 204A adds the despread inphase signals. The adder 204B adds the despread quadrature signals. The multipliers 205A and 205B multiplies result values from the adders 204A and 204B by the pilot walsh sequence Wp(t). Then, the integration circuits 206A and 206B integrate the resulting values from the multipliers 205A and 205B, which generates phase difference compensation signals. The squaring circuits 207A and 207B squares the resulting value from the integration circuits 206A and 206B. Pilot signal is recovered by combining the resulting values from the squaring circuits 207A and 207B.
Multipliers 211A and 211B multiply the baseband inphase signal and the baseband quadrature signal by the walsh data sequence Wd(t). Multipliers 212A and 212C multiply the resulting value from the multiplier 211A by the inphase pseudo noise sequence P.sub.I (t) and the negative quadrature pseudo noise sequence -P.sub.Q (t). Multipliers 212B and 212D multiply result value from the multiplier 211B by the inphase pseudo noise sequence P.sub.I (t) and the quadrature pseudo noise sequence P.sub.Q (t). Integration circuits 213A through 213D integrate the resulting values from the multipliers 212A through 212D. Multipliers 214A and 214D each multiply the resulting values from the integration circuits 213A and 213D by Acos.phi.. Multipliers 214B and 214C each multiply the resulting values from the integration circuits 213B and 213C by Asin.phi.. An adder 215A adds the resulting value from the multiplier 214A to the resulting value from the multiplier 214B. which recovers the inphase data signal. An adder 215B adds result from the multiplier 214C to result from the multiplier 214D, which recovers the quadrature data signal.
A general DS/CDMA communication system needs a pilot signal for the establishment and tracking of synchronization. Using the pilot signal, it is easy to implement receiver because of easy extraction of the phase difference compensation signal. However, it needs electric power and radio channel for transmitting the pilot signal, which reduces a accommodation capacity of the communication system.
To overcome these problems, in the conventional system, the pilot signal is used only in the forward channel transmission from the base station to the mobile station, and not in the backward channel transmission from the mobile station to the base station. This does not cause a reduction in the accommodation capacity. However, there is a problem in performance and a difficult implementation of the receiver.